As more and more liquid crystal display devices of superior quality are produced at low costs, the gate driver on array (GOA) technology has been widely used due to its advantages such as low costs and high integration.
However, in an existing GOA drive circuit, when trigger units of a plurality of GOA drive units are all triggered by start vertical signals (STV), since first K scan clocks (CKs) are activated during a high level period, they constantly stay in a high level. This weakens a potential at scan control signal point Q (as shown in FIG. 2) of each of first K scan control signals under a coupling effect of a bootstrap capacitor. As a result, a long time is necessary for first K gate lines to achieve a required high potential, thereby leading to poor charging, which further deteriorates display effects and quality of the display device.
In view of the foregoing, it is desirable to provide a new design of a GOA drive circuit for solving the above problem.